This nonprovisonal application claims priority under 35 U.S.C. xc2xa7119 (a) on Patent Application No. 2002-033340 filed in JAPAN on Feb. 12, 2002, which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to a negative voltage output charge pump circuit that generates from an input voltage a negative voltage for output.
2. Description of the Prior Art
FIG. 5 is a circuit diagram showing an example of a conventional negative voltage output charge pump circuit. The negative voltage output charge pump circuit 1a shown in this figure is so configured that, as a PMOS transistor P1 and NMOS transistors N1, N2, and N3 (all of the enhancement type) acting as switching devices are periodically turned on and off according to control signals S1 and S2, a first capacitor C1 is charged with an input voltage Vin fed in via an input terminal IN, and then the voltage charged in the first capacitor C1 is fed out as a negative voltage xe2x88x92Vin via an output terminal OUT.
Now, how a negative voltage is output in the configuration described above will be described in more detail. First, the control signals S1 and S2 are fed in so that the PMOS transistor P1 and the NMOS transistor N1 are turned on and the NMOS transistors N2 and N3 are turned off. When these control signals S1 and S2 are fed in, the input voltage Vin is applied to one end (the point A) of the first capacitor C1, and the ground potential is applied to the other end (the point B) of the first capacitor C1. Thus, the first capacitor C1 is charged until the potential difference between its terminals becomes equal to the input voltage Vin.
After completion of the charging of the first capacitor C1, the logical levels of the control signals S1 and S2 are so switched that the PMOS transistor P1 and the NMOS transistor N1 are turned off and the NMOS transistors N2 and N3 are turned on. As a result of this switching, the point A conducts through the NMOS transistor N3 to a ground terminal GND, and thus the potential at the point A drops from the level of the input voltage Vin to the ground potential.
Here, as a result of the charging, between the terminals of the first capacitor C1 appears a potential difference equal to the input voltage Vin, and therefore, when the above-mentioned drop in the potential at the point A occurs, the potential at the point B drops from the ground potential to a negative voltage xe2x88x92Vin. At this time, the point B conducts through the NMOS transistor N2 to the output terminal OUT, and therefore the electric charge in a second capacitor C2 moves to the first capacitor C1. As a result, the potential at the output terminal OUT drops to the negative voltage xe2x88x92Vin.
In a configuration like the one described above in which MOS transistors are used as switching devices, it is generally necessary to secure a backgate potential for the MOS transistors. The backgate potential of a MOS transistor needs to be lower than its channel potential. This is because, if the backgate potential of a MOS transistor is higher than its channel potential, a PN diode is formed between the backgate and the channel, and permits a current to flow from the backgate to the channel, causing malfunctioning.
For example, in a case where the negative voltage output charge pump circuit 1a configured as described above is formed on a p-type substrate so as to have a twin-well structure, all the NMOS transistors N1, N2, and N3 are formed on the p-type substrate. Thus, the substrate potential itself serves as the backgate potential. In this case, for the reason mentioned above, the p-type substrate needs to be biased at the lowest potential within the circuit so that the substrate potential is lower than the channel potential of the NMOS transistors N1, N2, and N3.
Here, the lowest potential within the circuit is the potential at the point B as observed when the negative voltage xe2x88x92Vin is generated at the output by the charge in the first capacitor C1. However, when the first capacitor C1 is in the process of being charged, the potential at the point B is equal to the ground potential. That is, the potential at the point B is not always the lowest. Accordingly, in the negative voltage output charge pump circuit la configured as described above, the backgates of the NMOS transistors N1, N2, and N3 are connected to the output terminal OUT, at which the negative voltage xe2x88x92Vin is present all the time.
It is true that the negative voltage output charge pump circuit 1a configured as described above outputs the desired negative voltage xe2x88x92Vin without the risk of malfunctioning in which currents flow from the backgates of the NMOS transistors to their channels.
However, the negative voltage output charge pump circuit 1a configured as described above requires extra operation to bias the p-type substrate at the lowest potential (the negative voltage xe2x88x92Vin at the output terminal OUT) within the circuit. This leads to increased loss of electric power.
Moreover, the negative voltage output charge pump circuit 1a configured as described above is prone to malfunctioning caused by a parasitic NPN-type multiple-collector transistor. FIG. 6 is a vertical sectional view showing an outline of the structure of the negative voltage output charge pump circuit 1a formed on a p-type substrate so as to have a twin-well structure.
As shown in this figure, the parasitic NPN-type transistors Q1 has its emitter at the point B, has its base at the p-type substrate SUB, and has its collectors at the n-type well of the PMOS transistor P1 and the source of the NMOS transistor N1.
When the potential at the output terminal OUT and the potential at the p-type substrate SUB are made low, the potential at the point B, which is the emitter of the parasitic NPN-type transistors Q1, drops to the level of the negative voltage xe2x88x92Vin. At this time, the p-type substrate SUB, which is the base of the parasitic NPN-type transistors Q1, is at the ground potential. Accordingly, the base-emitter section of the parasitic NPN-type transistors Q1 is forward-biased, permitting a current to flow from the collector to the emitter.
When this unintended current flows to the point B, it captures the electric charge that is supposed to be fed to the first capacitor C1 to generate the negative voltage xe2x88x92Vin. As a result, neither the potential at the p-type substrate SUB nor the potential at the output terminal OUT drops, and thus no negative voltage is generated. This is because the current that flows from the p-type substrate SUB to the point B corresponds to the base current of the parasitic NPN-type transistors Q1, and thus hfe times that current flows to the point B. Moreover, the potential at the n-type well W, which is one of the multiple collectors of the parasitic NPN-type transistors Q1, is higher than the potential at the output terminal OUT and the potential at the p-type substrate SUB, and this causes an accordingly large current to flow to the point B.
The above-described malfunctioning caused by the parasitic NPN-type transistors Q1 can be overcome by replacing the NMOS transistors N1 and N2, to which a negative voltage is applied, both with PMOS transistors.
FIG. 7 is a circuit diagram showing another example of a conventional negative voltage output charge pump circuit. When the negative voltage output charge pump circuit 1b shown in this figure is formed on a p-type substrate so as to have a twin-well structure, PMOS transistors P1, P2, and P3 are formed on an n-type well electrically separated from the p-type substrate, and the backgate of the n-type well is connected to a potential higher than that of its channel (in the figure, to the input voltage Vin).
It is true that the negative voltage output charge pump circuit 1b configured as described above causes no serious problem even when the potential at the above-mentioned channel drops to the level of the negative voltage xe2x88x92Vin, so long as it is designed to stand such a potential. Moreover, it is not necessary to lower the substrate potential to the level of the negative voltage xe2x88x92Vin as in the negative voltage output charge pump circuit 1a. 
However, in the negative voltage output charge pump circuit 1b configured as described above, its circuit configuration does not permit the gate voltage of the PMOS transistors P2 and P3 to be made lower than their drain voltage. Thus, when the PMOS transistors P2 and P3 are turned on, their lowest drain-source voltage is equal to their drain-gate voltage, i.e., their threshold voltage.
Let the above-mentioned threshold voltage be Vth. Then, the output voltage is equal to xe2x88x92(Vinxe2x88x922Vth), which means a voltage loss of 2Vth. For example, when Vin=3 V and Vth=0.7 V, the voltage that appears at the output terminal OUT is as low as xe2x88x921.6 V. In this way, while the negative voltage output charge pump circuit 1b configured as described above is free from malfunctioning caused by a parasitic device, it suffers from increased loss of electric power.
An object of the present invention is to provide a negative voltage output charge pump circuit that is free from malfunctioning caused by a parasitic device, that operates with low loss, and that can be produced at low costs.
To achieve the above object, according to the present invention, a negative voltage output charge pump circuit is provided with: a capacitor that, while being charged, receives, at one end thereof, a reference voltage and receives, at the other end thereof, a positive voltage relative to the reference voltage and that, while being discharged, has that other end thereof conducting to the reference voltage and has that one end thereof conducting to an output terminal; a first switching device that is kept on while the capacitor is being charged so as to apply the reference voltage to that one end of the capacitor; and a second switching device that is kept on while the capacitor is being discharged so as to make that one end of the capacitor conduct to the output terminal. Here, at least one of the first and second switching devices is of the depletion type.